• DocumentCode
    1696888
  • Title

    Simulation results of an efficient defect analysis procedure

  • Author

    Stern, Olaf ; Wunderlich, Hans-Joachim

  • Author_Institution
    Inst. of Comput. Structures, Siegen Univ., Germany
  • fYear
    34608
  • Firstpage
    729
  • Lastpage
    738
  • Abstract
    For obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavior. In this paper, a method is presented for computing the occurrence probabilities of certain defects and the realistic fault coverage for test sets. The method is highly efficient as a pre-processing step is used for partitioning the layout and extracting the defects ranked in the order of their occurrence probabilities. The method was applied to a public domain library where defects causing a complex faulty behavior are possible. The occurrence probability of these faults was computed, and the defect coverage for different test sets was determined
  • Keywords
    automatic testing; digital simulation; failure analysis; fault location; logic partitioning; logic testing; probability; defect coverage; efficient defect analysis; fault coverage; fault extraction; fault simulation; layout; occurrence probabilities; partitioning; preprocessing; public domain library; stuck-at fault model; zero defect level; Analytical models; Circuit faults; Circuit testing; Computational modeling; Electrical fault detection; Fabrication; Libraries; Logic circuits; Production; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1994. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-2103-0
  • Type

    conf

  • DOI
    10.1109/TEST.1994.528019
  • Filename
    528019