Title :
Automatic impedance control
Author :
DeHon, A. ; Knight, T., Jr. ; Simon, T.
Author_Institution :
Artificial Intelligence Lab., MIT, Cambridge, MA, USA
Abstract :
The authors describe circuits and techniques that provide automatic on-chip impedance matching between a series-terminated, low-voltage swing, CMOS I/O pad, and an external interconnect. The automatic impedance control technique employs a digitally controlled output impedance driver, a high-gain, low-voltage differential receiver, and an IEEE-1149.1-1990 compatible test access port. The techniques presented here design circuits that compensate for external environmental variations. A component to test these circuits uses a 0.8- mu m effective gate-length process. The test components exhibit 2-ns I/O latencies with 1-ns rise/fall times and match impedances between 30 and 100 Omega .<>
Keywords :
CMOS integrated circuits; compensation; digital integrated circuits; driver circuits; impedance matching; 0.8 micron; 1 ns; 2 ns; CMOS I/O pad; IEEE-1149.1-1990 compatible test access port; automatic impedance control technique; automatic on-chip impedance matching; digitally controlled output impedance driver; external environmental variations; external interconnect; high-gain receiver; low-voltage differential receiver; low-voltage swing; series-terminated; Automatic control; Circuit testing; Delay; Distributed parameter circuits; Driver circuits; Impedance matching; Inverters; Logic; Power transmission lines; Registers;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280013
