Title :
Leakage power reduction by dual-Vth designs under probabilistic analysis of Vth variation
Author :
Liu, Michael ; Wang, Wei-Shen ; Orshansky, Michael
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
Low-power circuits are especially sensitive to the increasing levels of process variability and uncertainty. In this paper we study the problem of leakage power minimization through dual Vth design techniques in the presence of significant Vth variation. For the first time we consider the optimal selection of Vth under a statistical model of threshold variation. Probabilistic analytical models are introduced to account for the impact of Vth uncertainty on leakage power and timing slack. Using this model, we show that the non-probabilistic analysis significantly (by 3×) underestimates the leakage power. We also show that in the presence of variability the optimal value of the second Vth must be about 30mV higher compared to the variation-free scenario. In addition, this model provides a way to compute the optimal value of the second Vth for a variety of process conditions.
Keywords :
CMOS integrated circuits; circuit optimisation; integrated circuit design; integrated circuit modelling; low-power electronics; probability; timing; CMOS designs; analytical models; dual-Vth designs; leakage power minimization; leakage power reduction; low-power circuits; optimal selection; probabilistic analysis; probabilistic timing model; process variability; statistical model; threshold variation; timing slack; Analytical models; Circuits; Leakage current; MOSFETs; Minimization; Power system modeling; Power system reliability; Threshold voltage; Timing; Uncertainty;
Conference_Titel :
Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
1-58113-929-2
DOI :
10.1109/LPE.2004.1349298
