Synthesis of Multiple Rail Phase Encoding Circuits

Multiple rail phase encoding communication protocol has several unexploited advantages over traditional encodings. The main impediment to its use is the absence of practical and scalable implementations of controllers for phase encoded data transmission.The paper shows that phase encoding controllers belong to a wide class of circuits which convert combinatorial codes to partial orders of events and vice versa. The conventional methods of control logic synthesis are not directly applicable to this class due to the combinatorial explosion of the controllers specification. The Conditional Partial Order Graph model introduced recently is inherently suitable for specification and synthesis of these controllers as demonstrated in this work.The main focus of the paper is generation of robust and scalable area-efficient circuits for multiple rail phase encoders, decoders and repeaters. However, the proposed methodology can be applied to the larger class of controllers operating in the same code-to-sequence mode, e.g. CPU controllers, NoC routers etc.