Accelerated Flexible Co-Processor Architecture for Crypto Information

The paper presented a core of AFPC (Accelerated Flexible Co-Processor Architecture for Crypto Information) architecture which was developed with respect to speed and flexibility of crypto information, including symmetric-key cipher algorithms and Hash functions. As to crypto units, we adopt a specific design which is reconfigurable. At the mean time, a set of new VLIW instructions that improve the efficiency of the analyzed algorithms are introduced. A number of algorithms were implemented on an architectural simulator and dedicated parts of the architecture were realized using Verilog to measure hardware parameters. Finally, in synthesis, the design is fabricated on 0.18um CMOS cells through Design Compiler tool, and the performance of this co-processor is compared with other hardware/software implementation. The results prove that AFPC can achieve relatively high performance in cipher algorithms processing.