Title :
Experimental measurement of a novel power gating structure with intermediate power saving mode
Author :
Kim, Suhwan ; Kosonocky, Stephen V. ; Knebel, Daniel R. ; Stawias, Kevin
Author_Institution :
Dept. of Electr. Eng., Seoul Nat. Univ., South Korea
Abstract :
A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 μm CMOS bulk technology. Our measurement results show that the additional intermediate power-mode allows us to cover various power-performance trade-off regimes, compared to conventional power gating structures.
Keywords :
CMOS digital integrated circuits; VLSI; integrated circuit design; low-power electronics; system-on-chip; CMOS bulk technology; active power consumption; clock gating; ground bounce; inductive noise; intermediate power saving mode; low-power high-performance VLSI; macros; power gating structure; power-performance trade-off; reliability design; system-on-chip design; virtual ground node; wake-up latency; CMOS technology; Clocks; Delay; Integrated circuit noise; Leakage current; Power dissipation; Power measurement; Power system reliability; System-on-a-chip; Threshold voltage;
Conference_Titel :
Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
1-58113-929-2
DOI :
10.1109/LPE.2004.1349301
