Scanning probe nanolithography using self-assembled monolayer for fabrication of single electron transistors

This research proposes a novel fabrication of silicon nanowire with a nanometric island between tunnel junctions for single electron transistor (SET). The scanning probe microscope (SPM)-based nanolithography (SPNL) using a field-enhanced anodization technique was performed at a surface of octadecylsilyl (ODS) monolayer deposited on a silicon wafer. The ODS monolayer composed of organosilane molecules was used as a resist mask for wet etching of nano-thick silicon dioxide film with BHF. The ODS monolayer was patterned nanometrically, attributed to the degradation of the organosilane molecules by scanning a conductive probe with a bias voltage between the ODS surface and probe. Using the SPNL with the ODS monolayer, we have succeeded in fabricating SETs comprising a nanometric Si wire with a quantum island between tunnel junctions. The silicon nanowire, with a width of 40 nm and a thickness of 80 nm, was entirely accomplished by rapid thermal oxidation and SPNL on a silicon-on-insulator wafer with an overcoat of ODS monolayer. A silicon island with 40 nm-squares was also located between two tunnel junctions at the center of the wire. After growing a 20 nm-thick SiO/sub 2/ on the nanowire for the gate oxide, the tunnel junction width was reduced. The electrical characteristic of the SETs was also examined in this paper.