VLSI Implementation of a Lattice Reduction Algorithm for Low-Complexity Equalization

MIMO transmissions (e.g., V-BLAST) have been widely adopted for high-rate high-performance communication systems. When the maximum likelihood (ML) or near-ML detector is employed, full receiver diversity is collected for V-BLAST systems at the cost of high complexity. Conversely, linear equalizers and successive interference cancellation equalizers have much lower complexity, but these equalizers degrade performance due to the loss of diversity. Lattice reduction (LR) techniques have been introduced to restore the diversity of low- complexity equalizers. In this paper we describe the architecture and results of the first VLSI implementation of the CLLL LR algorithm.