Title :
Efficient O(√n) BIST algorithms for DDNPS faults in dual port memories
Author :
Amin, A.A. ; Osman, M.Y. ; Abdel-Aal, R.E. ; Al-Muhtaseb, H.
Author_Institution :
King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
Abstract :
The testability problem of dual port memories is investigated. Architectural modifications which enhance testability with minimal overhead on both silicon area and device performance are described. New fault models for both the memory array and the address decoders are proposed and efficient O(√n) test algorithms are presented. The new fault models account for the simultaneous dual access property of the device. In addition to the classical static neighborhood pattern sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, Duplex Dynamic Neighborhood Pattern Sensitive faults (DDNPSF)
Keywords :
built-in self test; design for testability; fault diagnosis; fault location; memory architecture; random-access storage; BIST algorithms; Duplex Dynamic Neighborhood Pattern Sensitive faults; address decoders; array test algorithm; dual port memories; fault models; memory array; simultaneous dual access; static neighborhood pattern sensitive faults; test algorithms; testability; Built-in self-test; Circuit faults; Circuit testing; Decoding; Logic testing; Minerals; Petroleum; Random access memory; Read-write memory; Silicon;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.528032
