DocumentCode
1697219
Title
Concurrent engineering with DFT in the digital system: a parallel process
Author
Sanchez, Ralph
Author_Institution
Hughes Aircraft Co., Los Angeles, CA, USA
fYear
34608
Firstpage
879
Lastpage
886
Abstract
A highly parallel design process is a means to minimize the system design cycle time. Concurrent engineering principles applied to design and test attain dramatic cycle time reduction in systems with structurally tested ICs
Keywords
application specific integrated circuits; circuit CAD; design for testability; integrated circuit testing; minimisation; product development; ASIC test design; BIST; DFT; MCM; VLSI; boundary scan testing; concurrent engineering; cycle time reduction; design cycle time; design for test; parallel design; structurally tested IC; Airborne radar; Aircraft propulsion; Application specific integrated circuits; Built-in self-test; Circuit testing; Concurrent engineering; Digital systems; Process design; System testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1994. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-2103-0
Type
conf
DOI
10.1109/TEST.1994.528035
Filename
528035
Link To Document