Title :
A 16 Mb CMOS SRAM with a 2.3 mu m/sup 2/ single-bit-line memory cell
Author :
Sasaki, K. ; Ueda, K. ; Takasugi, K. ; Toyoshima, H. ; Yamanaka, T. ; Hashimoto, N. ; Ohki, N.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A 16-Mb CMOS SRAM (static random access memory) that uses a 2.3- mu m/sup 2/ single-bit-line poly-pMOS load memory cell is presented. A write/read architecture for a high-density poly-pMOS load (or poly-resistor load) single-bit-line cell is used. The single-bit-line cell reduces the cell area to two thirds that of a two-bit-line cell using the same metal process. The 16-Mb SRAM, a test chip for a 64-Mb SRAM, is fabricated in 0.25- mu m CMOS technology. The typical address access time is 15 ns at 2.5 V and 25 degrees C.<>
Keywords :
CMOS integrated circuits; SRAM chips; 0.25 micron; 15 ns; 16 Mbit; 2.5 V; CMOS SRAM; poly-pMOS load memory cell; single-bit-line memory cell; static random access memory; write/read architecture; CMOS technology; Current density; Degradation; Delay; Differential amplifiers; Feedback circuits; Pulse generation; Random access memory; Testing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280027
