A 16 Mb CMOS SRAM with a 2.3 mu m/sup 2/ single-bit-line memory cell

A 16-Mb CMOS SRAM (static random access memory) that uses a 2.3- mu m/sup 2/ single-bit-line poly-pMOS load memory cell is presented. A write/read architecture for a high-density poly-pMOS load (or poly-resistor load) single-bit-line cell is used. The single-bit-line cell reduces the cell area to two thirds that of a two-bit-line cell using the same metal process. The 16-Mb SRAM, a test chip for a 64-Mb SRAM, is fabricated in 0.25- mu m CMOS technology. The typical address access time is 15 ns at 2.5 V and 25 degrees C.<>