Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors

Asynchronous self-timed circuits which tolerate any delay variations are a feasible solution to timing-related problems while they suffer large energy dissipation due to large amount of their circuits. In future process technologies, it has been recognized that leakage power is a large factor in the total power dissipation. In this paper, we propose two leakage power reduction methods for m-out-of-n encoded circuits which operate based on the four-phase handshake protocol using multi-threshold-voltage transistors. One method is based on the traditional power gating technique which reduces leakage power by shutting off the power of idle circuits. Another method is to apply high-threshold-voltage transistors into the off-state transistors whose gate input signals are inactive in the idle phase. The evaluation results show that about 94% and 81% of the leakage power in the idle phase can be reduced.