Title :
Single-VDD and single-VT super-drowsy techniques for low-leakage high-performance instruction caches
Author :
Kim, Nam Sung ; Flautner, Krisztián ; Blaauw, David ; Mudge, Trevor
Abstract :
In this paper, we present a circuit technique that supports a super-drowsy mode with a single-VDD. In addition, we perform a detailed working set analysis for various cache line update policies for placing lines in a drowsy state. The analysis presents a policy for an instruction cache and shows it is as good as or better than more complex schemes proposed in the past. Furthermore, as air alternative to using high-threshold devices to reduce the bitline leakage through access transistors in drowsy caches, we propose a gated bitline precharge technique. A single threshold process is now sufficient. The gated precharge employs a simple but effective predictor that almost completely hides any performance loss incurred by the transitions between sub-banks. A 64-entry predictor with 3 bits per entry reduces the run-time increase by 78%, which is as effective as previous proposals that used content addressable predictors with 40 bits per entry. Overall, the combination of the proposed techniques reduces the leakage power by 72% with negligible (0.4%) run-time increase.
Keywords :
cache storage; leakage currents; low-power electronics; memory architecture; access transistors; architectural simulator; cache line control policy; cache line update policies; gated bitline precharge technique; low power; low-leakage high-performance instruction caches; on-chip caches; single threshold process; super-drowsy techniques; Dynamic voltage scaling; Energy consumption; Integrated circuit technology; Leakage current; Performance analysis; Performance loss; Proposals; Runtime; Threshold voltage; Voltage control;
Conference_Titel :
Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
1-58113-929-2
DOI :
10.1109/LPE.2004.1349307