Control strategies for chip-based DFT/BIST hardware

We present strategies for controlling on-chip design-for-test (DFT) and built-in self-test (BIST) circuitry under a partially distributed test control architecture. These include mechanisms for broadcasting control information from apt integrated TAP controller over an infernal test bus, techniques for creating symbolic descriptions of local decoders that employ this information to control test resources, and algorithms for encoding the bus information. The encoding algorithms minimize a two-level implementation of the integrated TAP controller and/or the distributed decoders. These control strategies are IEEE 1149.1 boundary scan standard compliant and are applicable to both simple and complex DFT/BIST methodologies including those that employ multifunction and/or reconfigurable test registers and reconfigurable scan chains