Title :
A 1.2 ns/1 ns 1 K*16 ECL dual-port cache RAM
Author :
Shin, H.J. ; Lu, P.F. ; Chin, K. ; Chuang, C.-T. ; Warnock, J.D. ; Franch, R.L.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
An experimental 1-k*16 ECL (emitter coupled logic) dual-port cache RAM block that has a read/write port and an independently accessible read-only port is presented. Multiples of this block can be used to construct a high-performance, large-capacity cache memory. This dual-port memory cell is constructed by adding a differential emitter-coupled sense circuit for the read-only port to the p-n-p-load (or SCR-type) bipolar read/write single-port cell. The p-n-p-load cell is chosen because of its smaller area and better soft-error immunity than other types of bipolar memory cells. The cache block is fabricated using a 0.8- mu m, trench-isolated, double-poly, self-aligned 3.6-V Si-bipolar technology with double metal layers and a W local-interconnection layer.<>
Keywords :
bipolar integrated circuits; buffer storage; elemental semiconductors; emitter-coupled logic; integrated memory circuits; random-access storage; silicon; 0.8 micron; 1 ns; 1.2 ns; 16 kbit; 3.6 V; ECL dual-port cache RAM; Si-bipolar technology; W local-interconnection layer; W-Si; differential emitter-coupled sense circuit; double metal layers; double poly self-aligned technology; dual-port memory cell; emitter coupled logic; large-capacity cache memory; p-n-p-load; read/write port; soft-error immunity; trench-isolated; Cache memory; Clamps; Decoding; Driver circuits; Energy consumption; High performance computing; Random access memory; Read-write memory; Thyristors; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280030
