Intelligent yield and speed prediction models for high-speed microprocessors

In this paper, neural networks based intelligent yield and speed prediction models are proposed for high-speed microprocessors. Parametric neural prediction model was applied to predict manufacturing yield using wafer level electrical test (ET) data. Three layered error back propagation (BP) networks were used for modeling, and they showed only 5.4% of prediction root mean square (RMS) error and it shows 41.09% improvement results as compared to statistical prediction model using multiple regression (MR) method. For final chip speed prediction, another neural process models are developed with similar methodology, and the average speed difference between prediction results and real CPU speed was only 1.7%. Through residual analysis, it was shown that proposed speed model fits to entire speed ranges without any bias. These prediction results can be applied to scrap schemes for wafer level die sort before packaging step and it helps to reduce manufacturing cost and time by minimizing undesirable packaging cost and time.