Title :
A 35 μW 1.1 V gate array 8×8 IDCT processor for video-telephony
Author :
Rambaldi, R. ; Ugazzoni, A. ; Guerrieri, Roberto
Author_Institution :
Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
Abstract :
We have designed and fabricated a low power IC to perform the inverse 8×8 DCT transform according to the CCITT precision specifications, suitable for portable video communication devices. Several design techniques have been used to reduce the power, such as a fast algorithm, an architecture that can exploit input signal correlation, and large amount of parallelism. The chip is fabricated in a triple metal 0.5 μm gate array CMOS technology. The maximum throughput is 400 Kpix/s at 1.1 V, and 27 Mpix/s at 3.3 V. The measured power consumption is 35 μW for typical image sequences in color QCIF format at 10 frames/sec with a 1.1 V power supply, making this device ideal for low power portable applications
Keywords :
CMOS logic circuits; digital signal processing chips; discrete cosine transforms; image sequences; inverse problems; logic arrays; parallel architectures; power integrated circuits; video signal processing; videotelephony; 0.5 micron; 1.1 V; 3.3 V; 35 muW; CCITT precision specifications; CMOS technology; IDCT processor; color QCIF format; fast algorithm; gate array; image sequences; input signal correlation; inverse DCT transform; low power IC; low power portable applications; maximum throughput; measured power consumption; parallel architecture; portable video communication devices; power reduction; power supply; video-telephony; videoconferencing; Algorithm design and analysis; CMOS technology; Discrete cosine transforms; Energy consumption; Image sequences; Power integrated circuits; Power measurement; Semiconductor device measurement; Signal design; Throughput;
Conference_Titel :
Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998 IEEE International Conference on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-4428-6
DOI :
10.1109/ICASSP.1998.678155
