An Efficient VLSI Architecture for Template Matching

In this paper, we describe a new special purpose VLSI architecture for template matching, based on a technique known as moment preserving pattern matching (MPPM). This technique first converts the given gray scale image and template into binary form using the moment preserving quantization method and then uses a pairing function to compute the similarity measure. The technique yields accurate results comparable to other approaches but involves simpler computations. The proposed architecture is systolic in nature and achieves a high degree of parallelism and pipelining. It is shown that the proposed architecture is much simpler, achieves higher speed, has a lower hardware complexity and utilizes lesser memory than other special purpose architectures for template matching.