Cascadable digital emulator IC for 16 biological neurons

Author

Prange, S.J. ; Klar, H.

Author_Institution

Tech. Univ. of Berlin, Germany

fYear

1993

Firstpage

234

Lastpage

235

Abstract

A cascadable digital fill-custom IC implemented in 1.5- mu m CMOS technology is described. The starting point of the circuit design is a 16-synapse building block. The 16-synapse building block is regarded as a row of a 16*16 synapse matrix. The postsynaptic signals are summed up serially. The sum of postsynaptic signals is added to the postsynaptic sum of a cascaded chip. This sum is fed to the feeding/linking multiplier of the Marburg model, whose output is connected to the neural output function consisting of another 16-synapse building block and a pulse generator. The shape and the delay of the output pulse are configurable in order to achieve a delayless cascadability and an adjustable temporal accuracy.<>

Keywords

CMOS integrated circuits; application specific integrated circuits; cascade networks; digital integrated circuits; neural chips; 1.5 micron; 16-synapse building block; CMOS technology; Marburg model; cascadable digital fill-custom IC; cascaded chip; digital emulator IC; feeding/linking multiplier; neural output function; postsynaptic signals; synapse matrix; CMOS digital integrated circuits; CMOS integrated circuits; CMOS technology; Circuit synthesis; Delay; Digital integrated circuits; Joining processes; Neurons; Pulse generation; Shape;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280035

Filename

280035