A new architecture for in-memory image convolution

A new memory-based architecture for real-time image convolution with variable kernels is proposed. The architecture exploits the highest possible bandwidth inherent in memory and achieves the fine-grain parallelism of computations inside the memory. Unlike existing approaches, the architecture ensures convolution with very large kernels under the real time constraints of video applications. It does not require external memory banks or large I/O count and features single chip VLSI implementation