DocumentCode :
1697493
Title :
Self-calibration techniques for a second-order multibit sigma-delta modulator
Author :
Fattaruso, J.W. ; Kiriaki, S. ; Warwar, G. ; de Wit, M.
Author_Institution :
Texas Instrum. Inc. Dallas, TX, USA
fYear :
1993
Firstpage :
228
Lastpage :
229
Abstract :
An oversampled modulator design that uses a second-order loop and a three-bit quantizer to exhibit low quantization noise is reported. Second-order loops are attractive because they are unconditionally stable and require only a third-order sinc filter in the decimation filter. Tone energy is significantly reduced in a multibit loop. In addition, a multibit quantizer avoids increased noise generation with input levels near full scale. The modulator uses digital self-calibration of the DAC (digital-to-analog coverter) capacitors to reduce their mismatch. High linearity and low noise are then simultaneously possible when random dynamic capacitor matching is used. The modulator is clocked at 6.144 MHz, and a 0.5-VRMS low-distortion sine wave at 2 kHz is applied at the input. The decimation filtering, with an oversampling ratio of 128-to-1, is performed by an external processor.<>
Keywords :
calibration; delta modulation; digital-analogue conversion; modulators; 6.144 MHz; DAC; decimation filter; digital self-calibration; low quantization noise; multibit loop; multibit sigma-delta modulator; oversampled modulator design; random dynamic capacitor matching; second-order loop; third-order sinc filter; three-bit quantizer; Capacitors; Clocks; Delta-sigma modulation; Digital modulation; Filtering; Filters; Linearity; Noise generators; Noise level; Quantization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
Type :
conf
DOI :
10.1109/ISSCC.1993.280037
Filename :
280037
Link To Document :
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