On synthesizing circuits with implicit testability constraints

The goal of test synthesis is to create a circuit which is completely testable under a design-for-test (DFT) methodology while meeting performance and area requirements. It includes such steps as testability design rule checking and automated repair of identified violations. Potential violations include clock and asynchronous circuitry which do not operate in a manner consistent with the chosen methodology and tools. Repair is performed by transforming the network through the insertion of additional logic to perform test functions (a scan chain, for example) and mapping this logic into the implementation technology, without affecting the original, system mode operation of the network. This paper discusses the concept of test synthesis constraints which embody the conditions under which the circuit must operate in order to be fully testable. Based on the constraints, the circuit is transformed using algorithms similar to those of automatic test pattern generation. Rather than adding entirely new hardware, existing system logic and connectivity is used to implement test functions wherever possible. Results produced by a prototype implementation indicate that test logic can be inserted into a network with very little performance or area overhead