Title :
A two-chip CMOS read channel for hard-disk drives
Author :
Negahban, M. ; Behrashi, R. ; Tsang, G. ; Abouhossein, H. ; Bouchaya, G.
Author_Institution :
Western Digital Corp., Irvine, CA, USA
Abstract :
Traditionally, the analog portion of disk-drive electronics is implemented in a high-performance bipolar technology. The authors demonstrate the feasibility of an all-CMOS solution with high-performance analog functions in 0.9- mu m CMOS to support data rates to 64 Mb/s. Reported CMOS supports a lower data rate. A typical block diagram of the analog portion of drive electronics includes the front-end pulse detector, data/clock recovery, and servo demodulator blocks. The data recovery and servo demodulator blocks have been demonstrated in a CMOS process. A programmable gain stage, filtering, and a pulse-detector supporting a 64-Mb/s data-rate read channel using 1,7 RLL code are described.<>
Keywords :
CMOS integrated circuits; demodulators; detector circuits; hard discs; 0.9 micron; 1,7 RLL code; 64 Mbit/s; data rates; data/clock recovery; drive electronics; front-end pulse detector; hard-disk drives; high-performance analog functions; programmable gain stage; pulse-detector; servo demodulator blocks; two-chip CMOS read channel; Bandwidth; CMOS technology; Delay; Dynamic range; Filtering; Frequency; Hard disks; Low pass filters; Pulse amplifiers; Resistors;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280042
