A low-power VLSI feature extractor for speech recognition

Author

Felici, M. ; Borgatti, M. ; Ferrari, A. ; Guerrieri, R.

Author_Institution

Dipt. di Elettronica Inf. e Sistemistica, Bologna Univ., Italy

Volume

5

fYear

1998

Firstpage

3061

Abstract

A low-power feature extraction chip computing cepstral coefficients from linear predictive analysis on one-bit quantized speech signals is presented and its VLSI implementation is evaluated. An isolated-word small-vocabulary speech recognizer based on these features has been developed. Its recognition accuracy is within 2% below a system based on standard linear predictive cepstral features. The power consumption of the feature extractor chip is 30 μW at 0.9 V

Keywords

CMOS digital integrated circuits; VLSI; cepstral analysis; feature extraction; prediction theory; quantisation (signal); speech recognition; 0.5 micron; 0.9 V; 30 muW; CMOS; cepstral coefficients; feature extractor chip; isolated-word small-vocabulary speech recognizer; linear predictive analysis; linear predictive cepstral features; low-power VLSI feature extractor; one-bit quantized speech signals; power consumption; recognition accuracy; speech recognition; Analog-digital conversion; Autocorrelation; Cepstral analysis; Energy consumption; Feature extraction; Personal digital assistants; Speech analysis; Speech recognition; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998 IEEE International Conference on

Conference_Location

Seattle, WA

ISSN

1520-6149

Print_ISBN

0-7803-4428-6

Type

conf

DOI

10.1109/ICASSP.1998.678172

Filename

678172