Reliability evaluations of chip interconnect in lead-free solder systems

Chip interconnect (solder to silicon) reliability is one of the critical elements in the qualification of flip-chip bumping technology. Since the interconnect materials, structures and processes vary in different bumping technologies, the strength and reliability must be evaluated for each design. As lead-free solders are used in the system, the intermetallics associated with the lead-free solders and the UBM (under bump metallurgy) has also influence on the interconnect reliability. In addition, the stress that an interconnect experiences during thermal cycling depends on the properties of the solder alloy used in the interconnect. Different solder alloys require different interconnect strengths to achieve good reliability in thermal cycling. This paper reports on a study of interconnect reliability by comparing the interconnect strength and the working stress in the interconnect during qualification and application. A simple stress model was developed to determine the interconnect stress during thermal cycling. A testing methodology was established for determining the interconnect strength. In this report, the reliability of several interconnect structures in several lead-free solder systems, including Sn/Ag, Sn/Ag/Cu and Sn/Cu solders and the Ni-Au and TiW-Cu UBMs were studied.