Prospects of gigascale integration (GSI) beyond 2003

The authors suggest that beyond 2003, further opportunities for GSI will be governed by a hierarchy of theoretical and practical limits whose levels can be codified as: (1) fundamental, (2) material, (3) device, (4) circuit, and (5) system. Theoretical limits are elucidated by plotting the average power dissipation during a binary switching transition of a logic gate P versus the corresponding gate delay time t/sub d/ and the reciprocal length squared of an interconnect versus the response time of the interconnect circuit. Using both the hierarchy of theoretical limits and the history of practical limits as guides, a one-billion-transistor chip is again projected by the year 2000 and the possibility of a one-trillion-transistor chip by the year 2020 is suggested.<>