A Novel BiST and Calibration Technique for CMOS Down-Converters

This paper presents a new digital calibration methodology that allows CMOS Gilbert cell down-converters to meet their block specifications under large process, temperature and power supply variations. The calibration method consists of a novel built-in self test for direct conversion receivers that is able to measure the gain, and the second and third order intermodulation products of the mixer. A random optimizer algorithm based on a least square error function provides digital control of the biasing circuit and the loads of the mixer. The gain and IIP3 are calibrated by regulating the current of the input differential pair and by switching the loads. IIP2 calibration is achieved by using a novel technique that consists of offset voltages cancellation in the switching pairs. The technique is validated by calibrating a 0.18 um CMOS mixer in several corner conditions.