• DocumentCode
    1698152
  • Title

    Associative architecture for fast DCT

  • Author

    Shain, Y. ; Akerib, A. ; Adar, R.

  • Author_Institution
    Associative Comput. Ltd., Raanan, Israel
  • Volume
    5
  • fYear
    1998
  • Firstpage
    3109
  • Abstract
    This paper discusses an associative processor architecture designed to meet the demands of real-time image processing applications. In a single chip, this architecture provides thousands of processors-one for each pixel, in the form of associative memory. This paper focuses on a generic, proprietary associative processor architecture and discusses implementing the discrete cosine transform (DCT) using processors based on this architecture. Associative Computing Ltd. has developed a commercial associative chip based on this architecture, and while the DCT implementation discussed refers to future generations based on this architecture, reference is made throughout to the company´s present processor. Processors based on our associative architecture can process the large amounts of data typically required in real-time imaging applications at a lower cost-performance ratio than conventional processors. The scalable nature of memory-based processor architecture allows developers to rapidly increase processing power without altering the fundamental processor, or system architecture. The underlying technologies used in the company´s present processor can significantly facilitate the development of associative processing as an alternative to conventional processing for video applications including compression and video editing
  • Keywords
    associative processing; digital signal processing chips; discrete cosine transforms; parallel architectures; real-time systems; video signal processing; Associative Computing Ltd.; associative processor architecture; commercial associative chip; cost-performance ratio; discrete cosine transform; fast DCT; generic proprietary associative processor architecture; real-time image processing applications; Associative memory; Computer architecture; Discrete cosine transforms; Image processing; Instruments; Memory architecture; Pipeline processing; Process design; VLIW; Video compression;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998 IEEE International Conference on
  • Conference_Location
    Seattle, WA
  • ISSN
    1520-6149
  • Print_ISBN
    0-7803-4428-6
  • Type

    conf

  • DOI
    10.1109/ICASSP.1998.678184
  • Filename
    678184