Memristor-based modified recoded-multiplicand systolic serial-parallel multiplier

In this paper, a modified recoded-multiplicand systolic serial-parallel multiplier using memristors has been proposed. Memristor; the newly found circuit element; was used for less area and enhanced performance. The presented multiplier uses the modified Booth to get a structure of n/2 cells. The multiplier architecture is described as an n-bit multiplicand and m-bit multiplier structure. The multiplier architecture implementation and delays have been presented and discussed as a unit of the material implication gate “IMPLY”.