Title :
6 ns cycle 256 kb cache memory and memory management unit
Author :
Heald, R.A. ; Holst, J.C.
Author_Institution :
Integraph Corp., Palo Alto, CA, USA
Abstract :
A cache and memory management unit (CAMMU) which accesses the various units in parallel and pipelines the results for 6-ns throughput with minimum latency is described. To fit two 5-ns 128-kb memories with 256 outputs each in a foundry ASIC (application-specific integrated circuit) process and still have area for the control logic and smaller memories, a four-transistor pseudo-static memory cell is used. Time-sharing data input circuits and sense amplifiers between the two cache memories further reduce area, and post-charge logic for word-line access and sensing gives 5-ns access time. This CAMMU uses postcharge logic in coordinated access of TLB, TAG, and cache.<>
Keywords :
application specific integrated circuits; buffer storage; storage management chips; 256 KB; 6 ns; CAMMU; TAG; TLB; access time; cache memory; foundry ASIC; four-transistor pseudo-static memory cell; latency; memory management unit; parallel access; pipelining; post-charge logic; sense amplifiers; time-sharing data input; word-line access; Application specific integrated circuits; Cache memory; Delay; Foundries; Logic circuits; Memory management; Pipelines; Technical Activities Guide -TAG; Throughput; Time sharing computer systems;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280072
