Fabrication of ultra-fine line circuits on PWB substrates

One of the greatest challenges facing the packaging industry at present is the availability of organic substrates capable of routing and interconnecting high I/O fine pitch area array flip chip. These substrates require line widths and spacing of 3.5 to 12 μm for flip chip systems applications supporting chip I/O densities of 5 K-10 K/cm² and pitch of 50 to 100 μm. The system-on-a-package (SOP) module being developed at the Packaging Research Center (PRC) at Georgia Tech is focused on providing lines and spaces in the 6 to 10 μm range and microvias in the 10 to 15 μm range to support these applications. The PRC has been evaluating low cost materials and processes by integrating them into the SOP substrates. These substrates demonstrate the very fine and ultra fine line widths and spaces necessary to meet next-generation interconnect density requirements. Line widths and spaces of 15 to 25 μm and microvia diameters of 50 μm on low-cost organic substrates has been demonstrated in the fabrication of SOP testbed prototypes. Processes for 10 μm fine lines and spaces coupled with 25 μm small microvia interconnect are currently being developed for inclusion in the next phase of PRC SOP prototype test beds. The PRC plans further exploration into developing low-cost processes capable of achieving line widths and spaces of 6 to 10 μm for inclusion into future SOP test bed prototypes. A fine line and width structure made of 4 μm copper lines on build-up laminate (FR-4) is discussed in this paper. Additionally, we present highlights of a novel stack-via technology that enables the wiring density necessary to meet future interconnect requirements as indicated in the SIA semiconductor roadmap.