Title :
A 1.71 M-transistor CMOS CPU chip with a testable cache architecture
Author :
Saito, Y. ; Shimazu, Y. ; Kobayashi, S. ; Shimizu, T. ; Matsuo, M. ; Ohtsuka, A. ; Shirai, K. ; Murata, H. ; Nishiwaki, Y. ; Fujioka, I. ; Nabeta, Y. ; Kanamoto, H. ; Hiraoka, S. ; Suzuki, T. ; Hinata, J. ; Shimotsuma, Y.
Author_Institution :
Mitsubishi Electric Corp., Hyogo, Japan
Abstract :
A CISC CPU chip for the business computer is described. It contains an integer unit (IU), a double-precision floating-point unit (FPU), an address generation unit (AGU), and a Harvard-style memory unit with cache. The memory includes two independent memory management units (DMMU and IMMU), an 8-kB D-cache, a 32-B store buffer (SB), and a bus-controller unit (BCU). An on-chip PLL (phase-locked loop) synchronizes external and internal clock edges with a skew of 1-ns. The chip is fabricated in a 0.8- mu m CMOS double-polysilicon double-metal technology. A 77- mu m/sup 2/ SRAM (static random-access memory) cell uses a high resistance load formed by the second polysilicon layer. The 16.3-mm*12.7-mm chip contains 1.71-M transistors. In 40-MHz operation, power consumption is 6 W with a 5-V supply. The design is verified by simulations at several levels, using a microsimulator for evaluating parallelism of a large horizontal microprogram.<>
Keywords :
CMOS integrated circuits; buffer storage; computer architecture; microprocessor chips; phase-locked loops; 0.8 micron; 40 MHz; 5 V; 6 W; CISC CPU chip; CMOS CPU chip; CMOS double-polysilicon double-metal technology; D-cache; Harvard-style memory unit; SRAM; address generation unit; bus-controller unit; clock edges; double-precision floating-point unit; integer unit; memory management units; microsimulator; on-chip PLL; power consumption; store buffer; testable cache architecture; Buffer storage; CMOS technology; Clocks; Energy consumption; Memory management; Parallel processing; Phase locked loops; Random access memory; Synchronization; Testing;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280073
