• DocumentCode
    1698468
  • Title

    Competing CMOS circuit techniques

  • Author

    Slager, J. ; Gudger, K. ; Williams, Tyson ; Heller, Loree ; Svensson, Christer ; Madden, Liam ; Allstot, David J. ; Yetter, J.

  • fYear
    1993
  • Firstpage
    80
  • Lastpage
    81
  • Abstract
    A summary on competing CMOS circuit techniques is presented. It is noted that, when the complete picture is examined (including gating, clocking, and testability), much more disagreement than agreement is evident among CMOS designers. The panel probes into the areas of disagreement for today´s megachips and those of the future.<>
  • Keywords
    CMOS integrated circuits; integrated circuit technology; integrated circuit testing; CMOS circuit techniques; clocking; gating; megachips; technological forecasting; testability; CMOS logic circuits; CMOS technology; Circuit noise; Clocks; Latches; Logic circuits; Logic design; Logic devices; MOS devices; Pulse inverters;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Print_ISBN
    0-7803-0987-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.1993.280075
  • Filename
    280075
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1698468