Low-power carry-select adder using adaptive supply voltage based on input vector patterns

Author

Suzuki, Hiroaki ; Jeong, Woopyo ; Roy, Kaushik

Author_Institution

Renesas Technol. Corp., Hyogo, Japan

fYear

2004

Firstpage

313

Lastpage

318

Abstract

Demands for the low power VLSI have been pushing the aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose adaptive supply voltage carry-select adder (CSA) based on the input vector patterns. A proposed level converter based on the complementary pass transistor logic (CPL) cancels out the delay penalty of level conversion. We achieved 26% power improvement on a 128-bit CSA prototype over a conventional design with same performance.

Keywords

VLSI; adders; carry logic; circuit simulation; delays; integrated circuit design; integrated circuit measurement; logic design; low-power electronics; power supply circuits; 128 bit; CPL; CSA prototype; adaptive supply voltage; adaptive supply voltage carry-select adder; complementary pass transistor logic; design methodologies; input vector patterns; level conversion delay penalty; level converter; low power VLSI; low-power carry-select adder; power consumption; power improvement; Adders; Circuits; Clocks; Design methodology; Energy consumption; Logic; Personal digital assistants; Propagation delay; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on

Print_ISBN

1-58113-929-2

Type

conf

DOI

10.1109/LPE.2004.1349357

Filename

1349357