DocumentCode :
1698774
Title :
Application adaptive energy efficient clustered architectures
Author :
Marculescu, Diana
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
2004
Firstpage :
344
Lastpage :
349
Abstract :
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by deep-submicron technologies can be alleviated by using a multiple voltage/multiple frequency island design style, otherwise called the globally asynchronous, locally synchronous (GALS) design paradigm. This paper proposes a clustered architecture that enables application-adaptive energy efficiency through the use of dynamic voltage scaling for application code that is rendered non-critical for the overall performance, at run-time. As opposed to task scheduling using dynamic voltage scaling (DVS) that exploits workload variations across applications, our approach targets workload variations within the same application, while on-the fly classifying code as critical or noncritical and adapting to changes in the criticality of such code portions. Our results show that application adaptive variable voltage/variable frequency clustered architectures are up to 22% better in energy and 11% better in energy-delay product than their non-adaptive counterparts, while providing up to 31% more energy savings when compared to DVS applied globally.
Keywords :
asynchronous circuits; clocks; computer architecture; dynamic scheduling; integrated circuit design; low-power electronics; microprocessor chips; pipeline processing; processor scheduling; synchronisation; DVS; GALS; application adaptive energy efficient clustered architectures; application adaptive variable voltage/variable frequency clustered architectures; application-adaptive energy efficiency; clock frequency; clustered architecture; deep-submicron technologies; die area; dynamic voltage scaling; energy efficiency; energy savings; energy-delay product; globally asynchronous locally synchronous design paradigm; low skew global clock signal distribution; multiple voltage/multiple frequency island design; on-the-fly code classification; performance noncritical application code; task scheduling; workload variations; Application software; Clocks; Computer architecture; Dynamic scheduling; Dynamic voltage scaling; Energy efficiency; Frequency; Hardware; Permission; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
1-58113-929-2
Type :
conf
DOI :
10.1109/LPE.2004.1349363
Filename :
1349363
Link To Document :
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