Title :
A 20 ns battery-operated 16 Mb CMOS DRAM
Author :
Yamauchi, H. ; Suzuki, T. ; Sawada, A. ; Iwata, T. ; Tsuji, T. ; Agata, M. ; Taniguchi, T. ; Odake, Y. ; Sawada, K. ; Ohnishi, T. ; Fukumoto, M. ; Fujita, T. ; Inoue, M.
Author_Institution :
Matsushita Electric Ind. Co. Ltd., Osaka, Japan
Abstract :
An address-multiplexed 16-Mb CMOS DRAM (dynamic random-access memory) that has RAS access time of 20 ns at 3.3 V and 36 ns at 1.8 V is described. Three circuit techniques are employed: (1) parallel column access redundancy combined with a current sensing address comparator; (2) a gate isolated sense amplifier with low threshold voltage; and (3) a short signal path architecture with a layout for the LOC package. Access speed degradation is minimized even at 1.8 V Vcc. A table summarizing process and performance for the device is presented.<>
Keywords :
CMOS integrated circuits; DRAM chips; redundancy; 1.8 to 3.3 V; 16 Mbit; 20 to 36 ns; CMOS DRAM; LOC package; address-multiplexed; battery-operated; current sensing address comparator; dynamic RAM; dynamic random-access memory; gate isolated sense amplifier; low threshold voltage; parallel column access redundancy; short signal path architecture; Circuits; Degradation; Delay effects; Lab-on-a-chip; MOS devices; Packaging; Quadratic programming; Random access memory; Switches; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280091
