A low-power DSP core architecture for low bitrate speech codec

Author

Okuhata, Hiroyuki ; Miki, Morgan H. ; Onoye, Takao ; Shirakawa, Isao

Author_Institution

Dept. of Inf. Syst. Eng., Osaka Univ., Japan

Volume

5

fYear

1998

Firstpage

3121

Abstract

A VLSI implementation of a low-power DSP is described, which is dedicated to the G.723.1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory. The proposed DSP architecture has been integrated in a total area of 7.75 mm² by using a 0.35 μm CMOS technology, which can operate at 10 MHz with the dissipation of 45 mW from a single 3 V supply

Keywords

CMOS digital integrated circuits; VLSI; digital arithmetic; digital signal processing chips; multiplying circuits; speech codecs; 0.35 micron; 10 MHz; 3 V; 45 mW; CMOS technology; DSP microarchitectures; G.723.1 low bitrate speech codec; VLSI implementation; dual multiply accumulators; low-power DSP core architecture; power dissipation; rounding; saturation; supply; two-banked on-chip memory; Bit rate; CMOS technology; Clocks; Decoding; Digital signal processing; Encoding; Filters; Frequency; Linear predictive coding; Speech codecs;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998 IEEE International Conference on

Conference_Location

Seattle, WA

ISSN

1520-6149

Print_ISBN

0-7803-4428-6

Type

conf

DOI

10.1109/ICASSP.1998.678187

Filename

678187