Title :
A 300 MHz 16 b BiCMOS video signal processor
Author :
Inoue, T. ; Goto, J. ; Yamashina, M. ; Suzuki, K. ; Nomura, M. ; Koseki, Y. ; Kimura, T. ; Atsumo, T. ; Motomura, M. ; Shih, B.S. ; Horiuchi, T. ; Hamatake, N. ; Kumagai, K. ; Enomoto, T. ; Yamada, H. ; Takada, M.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
A 300-MHz, 16-b video signal parallel-pipelined processor (VSP3) that features a vector parallel-pipelined architecture, 300-MHz arithmetic units, a 146-kb, 3-ns SRAM (static random-access memory), a PLL (phase-locked loop) and pass-transistor-type BiNMOS circuits is described. The block diagram of the VSP3 is presented, a timing of the parallel-pipelined vector processing is shown, and the H.261 coding algorithm is described.<>
Keywords :
BiCMOS integrated circuits; digital signal processing chips; image coding; image processing equipment; parallel architectures; pipeline processing; video equipment; video signals; 146 kbit; 16 bit; 3 ns; 300 MHz; BiCMOS; BiNMOS circuits; DSP chip; H.261 coding algorithm; PLL; SRAM; VSP3; arithmetic units; pass-transistor-type; phase-locked loop; static random-access memory; vector parallel-pipelined architecture; video signal processor; Adders; Arithmetic; BiCMOS integrated circuits; Capacitance; Clocks; Convolvers; Decoding; Logic circuits; Signal processing; Timing;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280094
