A real time P*64/MPEG video encoder chip

Author

Rao, S.K. ; Hatamian, M. ; Uyttendaele, M.T. ; Narayan, S. ; O´Neill, J.H. ; Uvieghara, G.A.

Author_Institution

Silicon Design Experts Inc., Lakewood, NJ, USA

fYear

1993

Firstpage

32

Lastpage

33

Abstract

A 10.5-GOPS video encoder chip is described which implements CCITT H.261, P*64, and MPEG (Motion Picture Experts Group) (P-frame) encoding algorithms (including exhaustive motion estimation) at rates up to 30 frames/s with a resolution of up to 352*288 pixels per frame (CIF format). The chip accepts input video through either a video bus or a 16-b host bus and produces the final encoded bit stream in its output FIFO. A completely self-contained and glueless interface in this chip makes it possible to directly connect it to industry standard DRAM chips (1 MB) needed for frame store. The block diagram of the encoder chip is shown, and the characteristics of the major modules are listed.<>

Keywords

CMOS integrated circuits; digital signal processing chips; image coding; image processing equipment; motion estimation; real-time systems; video signals; 101376 pixels; 288 pixels; 352 pixels; CCITT; CIF format; DRAM chip connection; DSP chip; H.261; MPEG; Motion Picture Experts Group; P*64; exhaustive motion estimation; frame store; glueless interface; output FIFO; real time; video encoder chip; Chromium; Communication system control; Discrete cosine transforms; Encoding; Engines; Hardware; Motion estimation; Quadratic programming; Quantization; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280096

Filename

280096