• DocumentCode
    1698993
  • Title

    An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes

  • Author

    Gorjiara, Bita ; Bagherzadeh, Nader ; Chou, Pai

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Irvine, CA, USA
  • fYear
    2004
  • Firstpage
    381
  • Lastpage
    386
  • Abstract
    Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage scaling in each on-chip core individually, many on-chip voltage regulators must be used. However, the limitations in implementation of on-chip inductors can reduce the efficiency, accuracy and the number of voltage modes generated by regulators. Therefore the future voltage scheduling algorithms must be efficient, even in the presence of few voltage modes; and fast, in order to handle complex applications. Techniques proposed to date need many fine-grained voltage modes to produce energy efficient results and their quality degrades significantly as the number of modes decreases. This paper presents a new technique called Adaptive Stochastic Gradient Voltage and Task Scheduling (ASG-VTS) that quickly generates very energy efficient results irrespective of the number of available voltage modes. The results of comparing our algorithm to the most efficient approaches (RVS and EE-GLSA) show that in the presence of only four valid modes, the ASG-VTS saves up to 26% and 33% more energy. On the other hand, other approaches require at least ten modes to reach the same level of energy saving that ASG-VTS achieves with only four modes. Therefore our algorithm can also be used to explore and minimize the number of required voltage levels in the system.
  • Keywords
    processor scheduling; real-time systems; stochastic processes; system-on-chip; thin film inductors; voltage regulators; ASG-VTS; EE-GLSA; RVS; SoC; adaptive stochastic gradient voltage and task scheduling; complex systems; dynamic voltage scaling; embedded systems; energy efficiency; on-chip cores; on-chip inductors; on-chip voltage regulators; processing cores; real-time systems; single chip; voltage modes; voltage scaling algorithm; voltage scheduling algorithms; Algorithm design and analysis; Dynamic voltage scaling; Embedded system; Energy efficiency; Inductors; Iterative algorithms; Real time systems; Regulators; Scheduling algorithm; Space exploration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
  • Print_ISBN
    1-58113-929-2
  • Type

    conf

  • DOI
    10.1109/LPE.2004.1349370
  • Filename
    1349370