A 1 Mb/s digital subscriber line transceiver signal processor

A monolithic custom digital signal processor which satisfies both the US and the European standards for HDSL (high-bit-rate digital subscriber line) transmission is presented. The architecture of an HDSL transceiver is shown. At the receiver, the ADC (analog-to-digital converter) samples the signal once per symbol period. The transmit energy is removed using an echo canceller. The resulting receive energy is then prefiltered and sent to the feedforward equalizer (FFE). The FFE provides gain and removes any precursor intersymbol interference (ISI). The decision-feedback equalizer then removes the postcursor ISI. The resulting data are sliced into a symbol decision and error value.<>