Title :
A 1 Mb/s digital subscriber line transceiver signal processor
Author :
Kuczynski, M.A. ; Lao, W. ; Dong, A.M. ; Wong, B.C. ; Nicholas, H.T. ; Itri, B.A. ; Samueli, H.
Author_Institution :
PairGain Technol., Cerritos, CA, USA
Abstract :
A monolithic custom digital signal processor which satisfies both the US and the European standards for HDSL (high-bit-rate digital subscriber line) transmission is presented. The architecture of an HDSL transceiver is shown. At the receiver, the ADC (analog-to-digital converter) samples the signal once per symbol period. The transmit energy is removed using an echo canceller. The resulting receive energy is then prefiltered and sent to the feedforward equalizer (FFE). The FFE provides gain and removes any precursor intersymbol interference (ISI). The decision-feedback equalizer then removes the postcursor ISI. The resulting data are sliced into a symbol decision and error value.<>
Keywords :
application specific integrated circuits; digital communication systems; digital signal processing chips; echo suppression; equalisers; intersymbol interference; subscriber loops; transceivers; 1 Mbit/s; ADC; European standards; HDSL; ISI; US standards; decision-feedback equalizer; digital subscriber line; echo canceller; error value; feedforward equalizer; high-bit-rate; monolithic custom digital signal processor; precursor intersymbol interference; symbol decision; transceiver signal processor; Copper; DSL; Data acquisition; Signal processing; Transceivers;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280099
