DocumentCode
1699119
Title
A Quaternary Decision Diagram Machine and the Optimization of its Code
Author
Sasao, Tsutomu ; Nakahara, Hiroki ; Matsuura, Munehiro ; Kawamura, Yoshifumi ; Butler, Jon T.
Author_Institution
Kyushu Inst. of Technol., Iizuka
fYear
2009
Firstpage
362
Lastpage
369
Abstract
We show the advantage of quarternary decision diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.
Keywords
decision diagrams; optimisation; logic function; optimization; quaternary decision diagram machine; Binary decision diagrams; Boolean functions; Data structures; Input variables; Logic functions; Microprocessors; Testing; BDD; MDD; PLC; code optimization; logic simulation; programmable logic controller;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on
Conference_Location
Naha, Okinawa
ISSN
0195-623X
Print_ISBN
978-1-4244-3841-9
Electronic_ISBN
0195-623X
Type
conf
DOI
10.1109/ISMVL.2009.35
Filename
5010426
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