Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T

This paper describes a 5-transistor (5T) SRAM bitcell that uses a novel asymmetric sizing approach to achieve increased read stability. Measurements of a 32 kb 5 T SRAM in a 45 nm bulk CMOS technology validate the design, showing read functionality below 0.5 V. The 5 T bitcell has lower write margin than the 6 T, but measurements of the 45 nm 5 T array confirm that a write assist method restores comparable writability with a 6 T down to 0.7 V.