An architectural study of a digital signal processor for block codes

Author

Drescher, Wolfram ; Mennenga, Menno ; Fettweis, Gerhard

Author_Institution

Mobile Commun. Syst., Tech. Univ. Dresden, Germany

Volume

5

fYear

1998

Firstpage

3129

Abstract

This paper examines architectural issues for a domain specific digital signal processor (DS-DSP) which is capable of fast decoding of block codes. In real time systems it was not possible before to employ common processors for this task because of a lack of architectural and arithmetical support. We proposed solutions for the arithmetical problem in previous work. In this paper we focus on architectures for implementation of different block decoding algorithms on a new DS-DSP architecture. The paper also contains benchmarks for our architecture for some selected codes and compares our DS-DSP to common digital signal processors (DSP) and dedicated logic solutions

Keywords

BCH codes; block codes; decoding; digital signal processing chips; parallel architectures; BCH decoding algorithm; DS-DSP architecture; arithmetical problem solution; block codes; block decoding algorithms; data manipulation; dataflow requirements; datapath architecture; dedicated logic solutions; digital signal processors; domain specific digital signal processor; fast decoding; parallel architecture; real time systems; Application software; Arithmetic; Block codes; Computer architecture; Decoding; Digital signal processing; Digital signal processors; Logic; Mobile communication; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998 IEEE International Conference on

Conference_Location

Seattle, WA

ISSN

1520-6149

Print_ISBN

0-7803-4428-6

Type

conf

DOI

10.1109/ICASSP.1998.678189

Filename

678189