A microcontroller IP generator for SOC platform

In this paper, a microcontroller IP generator, called VENUS, is presented. According to user´s functional specification such as an 18051 assembly language program, a microcontroller IP generator can produce a synthesizable microcontroller core and its in-circuit emulator core with minimized cost by only implementing the necessary instructions, the necessary operations of ALU, and the necessary peripherals automatically. IP cores are represented as a synthesizable Verilog HDL (Hardware Description Language) program. Furthermore, users can add other instructions and peripherals such as 18255 to match the users requirements. Therefore, the IP generator can generate the microcontroller rapidly to reduce the time-to-market.