A sliding IF receiver for mm-wave WLANs in 65nm CMOS

This paper presents a fully integrated receiver for mm-wave WLANs comprising LNA, RF mixer, quadrature IF mixers, local oscillator plus output stage for characterization, in 65 nm CMOS. The IF frequency set to 1/3 the RF frequency slides according to the received frequency. The architecture choice allows running the quadrature VCO around 20 GHz. A Phase Noise of -115 dBc/Hz @ 10 MHz offset from an equivalent LO at RF carrier is achieved with 36 mW power consumption and 12.5% frequency tuning range. The design of building blocks is discussed in details. Implemented prototypes use low-power digital devices and other measured performances are: 28 dB peak gain, 9 dB noise figure, 5 GHz RF bandwidth, -26 dBm 1-dB compression point, Gt 60 dB IRR. Total Power consumption is 80 mW from 1.5 V supply.