Title :
A 2.2 GHz programmable DLL-based frequency multiplier for SOC applications
Author :
Cheng, Kuo-Hsing ; Shu-Ming Chang ; Lo, Yu-Lung ; Jiang, Shu-Yu
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
Abstract :
In this paper, a DLL-based frequency multiplier is proposed. No LC-tank and ring oscillator are used in the proposed design such that the power dissipation and chip area are drastically reduced. Moreover this multiplier doesn´t require external component and it is primarily intended for ASIC design. The HSPICE simulation results are based upon TSMC 0.18 μm 1P6M N-well CMOS process at 1.8 V power supply. The simulation results show that the DLL can operate from 350 to 550MHz and the frequency multiplier synthesize frequency from 350MHz to 2.2GHz. The proposed frequency multiplier possess the programmable function, and the output clock frequency is 1×, 2× and 4× of an input reference clock. Each different clock frequency, the power dissipation all less than 7mW and the cycle-to-cycle jitter is less than 33ps.
Keywords :
CMOS digital integrated circuits; SPICE; circuit simulation; delay lock loops; frequency multipliers; low-power electronics; phase detectors; programmable circuits; system-on-chip; timing jitter; 1.8 V; 2.2 GHz; ASIC design; DLL-based frequency multiplier; HSPICE simulation; N-well CMOS process; SOC application; charge pump; cycle-to-cycle jitter; edge combiner circuit; first order loop filter; low power consumption; phase detector; phase selector; programmable frequency multiplier; programmable local oscillator; voltage controlled delay line; Application specific integrated circuits; CMOS process; Clocks; Filters; Frequency synthesizers; Jitter; Phase locked loops; Power dissipation; Ring oscillators; Voltage-controlled oscillators;
Conference_Titel :
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8637-X
DOI :
10.1109/APASIC.2004.1349409
