DocumentCode :
1700094
Title :
An 8-bit 250MSPS CMOS pipelined ADC using open-loop architecture
Author :
Koo, Ja-Hyun ; Kim, Yun-Jeong ; Kim, Sin-Hu ; Yun, Won-Joo ; Lim, Shin-Li ; Kim, Suki
Author_Institution :
Dept. of Electron. Eng, Korea Univ., Seoul, South Korea
fYear :
2004
Firstpage :
94
Lastpage :
97
Abstract :
This paper describes some design techniques for high speed and low power pipelined 8-bit 250MSPS ADC. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 250MHz sampling rate, measurement results show that the power consumption is 150mW including digital logic with 1.8V power supply. And the proposed ADC achieves 38dB (SNDR) with input frequency up to 125-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a 0.18 μm 6-Metal 1-Poly CMOS process and occupies an area of 900 μm × 500 μm.
Keywords :
CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; low-power electronics; pipeline processing; 1.8 V; 150 mW; 8 bit; CMOS pipelined ADC; cascade structure; data coding algorithm; die area; distributed THA; high speed ADC; low power ADC; open-loop architecture; redundancy; signal reducing technique; zero-crossing point generation method; CMOS logic circuits; Energy consumption; Frequency; Optimization methods; Pipelines; Power amplifiers; Power generation; Power measurement; Power supplies; Sampling methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8637-X
Type :
conf
DOI :
10.1109/APASIC.2004.1349416
Filename :
1349416
Link To Document :
بازگشت