A phase detector for 12.5Gbps clock and data recovery with optimal detection

We propose a phase detector using a matched filter that maximizes the performance for a given input noise condition. The matched filter performs optimal detection that maximizes the signal-to-noise ratio (SNR) at the sampling instant. The phase detector is designed for a 12.5 Gbps clock-and-data recovery (CDR) circuit. Through optimal detection, the system rejects various types of noise, such as narrowband colored noise or additive white noise. The performance of the proposed phase detector is compared with a typical one through simulation. A delay-locked loop (DLL)-based clock recovery circuit is also implemented with the proposed phase detector and shows stable lock-in operation with the data SNR as low as 4.69 dB. It also shows 2.2 ps of root mean square (RMS) clock jitter when the second harmonic clock signal leakage degrades the data SNR to 5 dB.