A high resolution, wide range digital impedance controller for high-speed SRAM interface

Author

Kim, Tae-Hyoung ; Cho, Uk-Rae ; Byun, Hyun-Guen

Author_Institution

Memory Div., Samsung Electron., South Korea

fYear

2004

Firstpage

120

Lastpage

123

Abstract

This paper describes a digital impedance controller (DIC) for high-speed signal interface. The proposed DIC provides the wide range impedance control covering from 23Ω to 140Ω with 3.29% maximum quantization error. The maximum quantization error of the proposed DIC is +2.26% with RQ ranging from 23Ω to 53Ω the same range covered by conventional scheme. High-resolution and wide range impedance control are implemented by using automatic gate voltage optimization. The data input valid window is 623ps at 0.75±200mV and maximum eye open is 641mV meaning about 10% improvement at 1.5Gbps/pin DDR3 SRAM interface.

Keywords

SRAM chips; device drivers; digital control; electric variables control; peripheral interfaces; quantisation (signal); 23 to 140 ohm; automatic gate voltage optimization; digital impedance controller; high resolution wide range controller; high-speed SRAM interface; high-speed signal interface; maximum quantization error; off-chip drivers; pull-down driver; timing diagram; wide range impedance control; Automatic control; Bandwidth; Digital control; Impedance; Quantization; Random access memory; Resistors; Signal resolution; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8637-X

Type

conf

DOI

10.1109/APASIC.2004.1349424

Filename

1349424